The present invention discloses a method and system for clock and carrier recovery in a wireless communication system. More particularly, the present invention discloses a method and system for clock and carrier recovery in a direct sequence spread spectrum communication system.
In a typical wireless spread spectrum data communication system, the transmitter accepts a bit stream from a source and encodes it into a signal constellation point commonly known as a symbol. The signal constellation is a set of message points corresponding to the set of bits to be transmitted. The standard modulation techniques used for forming the symbol are Binary Phase Shift Keying (BPSK) and Quadrature Phase Shift Keying (QPSK). A sampled spreading sequence (for example a Barker Sequence) lasting over one symbol period is multiplied by the symbol to be transmitted to generate the samples of the signal to be transmitted in the baseband. The resulting samples are then fed to a Digital to Analog Converter (DAC) to generate the baseband analog signal. This analog signal is filtered to meet the required spectral mask and then fed to an up-converter, where a Radio Frequency (RF) carrier is modulated by the analog baseband signal. The output is then filtered and transmitted by means of an antenna. Clocks used for the DAC and the up-converter are derived from a common master clock to avoid non-coherency.
The signal is then transmitted through the channel and is received by the receiver. The signal is subjected to multi-path, thermal noise, co-channel and adjacent channel interferences while traveling through the channel. The receiver, after receiving the waveform, reverses the processing done on the signal at the transmitter to get the original signal that was generated by the signal source. The process involves down-conversion of the received RF signal to the baseband and then sampling the baseband analog signal by an Analog to Digital Converter (ADC). The output from the ADC is fed to the baseband processing engine for recovering the bit stream from the received quantized samples. At the receiver also, the clocks for the ADC and the down-converter are derived from a common master oscillator for clock coherency. The received baseband signal has clock and carrier offsets as the transmit and receive clock sources are different. The transmit and receive clocks can vary independently around their nominal values. The clock variation is caused mainly by the crystal frequency drift, which is susceptible to ambient temperature fluctuation, aging and other imperfections. These variations lead to a clock error, which is the difference between the transmit and the receive clocks. This clock error is expressed in terms of a normalized sampling rate error between the transmitter and receiver. The receiver has to estimate and compensate for these offsets in order to successfully decode the bit stream.
As a result of the imperfections and inaccuracies mentioned above, there is an offset in the sampling rates of the transmitter DAC and the receiver ADC. Further, the imperfections in the local oscillators, used for up-conversion and down-conversion respectively, result in a carrier offset. The carrier offset, if left uncompensated, results in a continuous rotation in the signal constellation. This offset needs to be compensated for an error-free decision at the receiver. Thus, clock and carrier recovery is an essential process in the receiver. The receiver needs to estimate and track the clock error in the presence of the imperfections and the fluctuations mentioned in the previous paragraph.
In most of the data communication systems, a Phase Locked Loop (PLL) performs clock and carrier recovery. However, the PLL has its limitations. Traditionally used PLLs suffer from problems like lock-in and pull-in range limitations, and trade-offs between accuracy and convergence time. Analog PLLs also suffer from inflexibility and difficulty in implementation unlike the PLLs implemented in full software i.e. implementation using a Digital Signal Processor (DSP), or in digital hardware i.e. implementation using a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC). Further, the performance accuracy of PLLs is limited by the precision of the analog devices used in the PLL, the device noise and the variation in the performance due to temperature fluctuations and aging. In addition to this, it is difficult to integrate PLLs with digital hardware for single chip implementation.
An all-digital carrier recovery is, therefore, much superior to the analog implementation. The performance of the digital implementation is also superior and more precise because its performance depends only on the noise in the input signal. Most of the schemes in all-digital implementation are based on a digital PLL having a Numerically Controlled Oscillator (NCO), digital loop filter and digital hardware to generate control signal for input to the NCO.
U.S. Pat. No. 5,361,276 entitled “All Digital Maximum Likelihood Based Spread Spectrum Receiver” granted to AT&T Bell Laboratories, NJ, USA filed on Sep. 13, 1993 discloses a spread spectrum receiver that uses a NCO to generate phase correction and overall frequency correction of the received signal. The receiver also comprises a digital frequency offset correction device for modifying the digital signal in accordance with a frequency correction term to correct the frequency offset in the received analog signal. In addition to this, WIPO Publication number 2001/50631A2 titled “Carrier Tracking Loop For Direct Sequence Spread Spectrum Systems” of Thomson Licensing S.A., France filed on Dec. 22, 2000 discloses a Carrier Tracking Loop (CTL) that is a phase error estimator for receiving the output symbol data. Further, a CTL phase error signal is generated based on the rotation of the spread-spectrum signal, and another CTL is used for generating the counter-rotating signal based on the CTL phase error signal.
Both the patents mentioned above use a NCO in their implementation. These are, therefore, digital translations of the analog counterpart of the PLL. Hence, these implementations also suffer from the traditional built-in problems with PLLs.
Some other methods that use Fast Fourier Transform (FFT) for carrier offset estimation and a frequency synthesizer for correction of LO (Local Oscillator) frequency have been proposed. European Patent number 892,528A2 titled “Carrier recovery for DSSS signals” granted to Nokia Mobile Phones Ltd., Espoo, Finland presents a device and a method for detection of direct sequence spread spectrum (DSSS) clocks using pseudo-random noise (PN) modulation when offsets are present in the carrier frequency. This is achieved by means of calculations using the Fast Fourier Transform (FFT).
The disadvantage of using the above-mentioned approach is that it is complex to implement and expensive in terms of the number of calculations needed. Thus, this scheme requires an expensive synthesizer with a fine enough frequency resolution to correct the carrier offset.
From the above discussion, it is apparent that there is a need for an all-digital scheme that is easy to implement and does not require extra digital hardware (such as the NCO, loop filter and the like). Further, the scheme should be easily implemented both in software (for example, using a digital signal processor) and in hardware (for example, using an FPGA or an ASIC). There is also a need for a system that is devoid of complex and expensive operations (like the FFT) and is efficient in correcting the carrier offset without disturbing the local oscillator.